Field
The present invention relates to the field of electronic device design, development, and production. More specifically, embodiments herein relate to electronic computer-aided design (“ECAD”) tools and methods of producing electronic devices and prototypes for such devices.
Description of the Related Art
Today's processor core or other large IC design projects generally involve many contributors, working in collaboration through complex processes. In small companies, the design process may include purchasing intellectual property use rights for most of the parts, and the design of the new section may be only a small part of the total chip both by area and by complexity. In a large company, different groups may be responsible for various different aspects of the design: for example, one for arithmetic functional unit design, another for cache designs, another for memory and I/O interface, another for the instruction interpretation section, etc. A major task is the continuous migration of these contributions to the next silicon process level.
Whether in a small company or large company setting, the technical challenges in mixing and matching sections of designs are significant. As an example, logic sections are often designed using CMOS, memory sections may be designed mainly using NMOS and/or/both PMOS. The characteristics of NMOS circuits are that at logic “0” the lines have low impedance; at logic “1” the lines have high impedance. This causes two problems. The first problem is that in NMOS switching to “0” is fast, however switching to “1” takes relatively long time as one is charging a high impedance line. In PMOS it is the same situation except that now “1” has the low impedance and “0” the high impedance and now discharging the line takes long time. However either of circuit types, PMOS or NMOS are very sensitive to; noise, cross talk and interference at the time the lines that are at the high impedance state.
CMOS solves the problem by just clamping together two circuits one NMOS, one PMOS and thus doubling the amount of transistors. In return CMOS gets fast level change at either 0=>1 or 1=>0 which doubles or even may triple the circuit speed. In addition the lines are at low impedance at logic “0” and at logic “1” state which provides for great noise immunity and high line cross talk barrier. Integrating a system that has some CMOS and some NMOS/PMOS section is a “zoo keeper's” dilemma, as the NMOS/PMOS modules do not tolerate the noise level that CMOS can handle.
ECAD tools are often used by design teams to manage the complex design of new electronic devices. However a significant portion of those ECAD design tools, rather than simplify the design process, may significantly complicate the process by imposing design rule limitations at the behest of various “stakeholders” which include the company's logic, testing and electronics standards department, the foundry's production and test rules, various ECAD simulation (SPICE, etc.). Though such tools are useful, some existing ECAD tools may effectively impose “ECAD design rules cages” that limit the engineers' freedom. In some cases, in particular, attempting to block bad designs ideas from entering into the design arena through stakeholder design rules methods also keep the good ideas out. As an example an engineer may not be allowed, by stakeholder rules, to logically simulate a combinatorics circuit until all electronic rules (layout, SPICE, clock distribution, wire length, etc.) have been applied. A problem is that in current ECAD systems the stakeholder rules may be applied en masse and too early in the design process and limit the designer's capability of obtaining logic simulation results prior to finishing any and all conceivable design inputs.
To increase the efficiency of the design process, prototypes are often used in the design and evaluation of devices under development. Such prototypes may, nevertheless, be themselves be quite expensive and difficult to design, produce, and test. Moreover, such prototypes may lack flexibility in making alterations and modifications needed to advance the production design.
Power usage and consumption of the electronic devices present additional challenges to the electronic device designers. High power consumption of electrical devices may be considered in the context of three major problems: One problem is just the shear cost or availability in wireless devices of the electric power, the second problem is associated with the electrical distribution of the power to the packages containing the silicon dies. A third problem is in some respects the largest: How to get rid of all that power that after the logic and memory circuits got through with it has now turned into heat.